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Creators/Authors contains: "Ramanan, Paritosh"

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  1. —Stochastic optimization problems in large-scale multi-stakeholder networked systems (e.g., power grids and supply chains) rely on data-driven scenarios to encapsulate complex spatiotemporal interdependencies. However, centralized aggregation of stakeholder data is challenging due to the existence of data silos resulting from computational and logistical bottlenecks. In this paper, we present SplitVAE, a decentralized scenario generation framework that leverages variational autoencoders to generate high-quality scenarios without moving stakeholder data. With the help of experiments on distributed memory systems, we demonstrate the broad applicability of SplitVAEs in a variety of domain areas that are dominated by a large number of stakeholders. Furthermore, these experiments indicate that SplitVAEs can learn spatial and temporal interdependencies in large-scale networks to generate scenarios that match the joint historical distribution of stakeholder data in a decentralized manner. Lastly, the experiments demonstrate that SplitVAEs deliver robust performance compared to centralized, state-ofthe-art benchmark methods while significantly reducing data transmission costs, leading to a scalable, privacy-enhancing alternative to scenario generation. 
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    Free, publicly-accessible full text available December 15, 2025
  2. The Von Neumann bottleneck, a fundamental chal- lenge in conventional computer architecture, arises from the inability to execute fetch and data operations simultaneously due to a shared bus linking processing and memory units. This bottleneck significantly limits system performance, increases energy consumption, and exacerbates computational complex- ity. Emerging technologies such as Resistive Random Access Memories (RRAMs), leveraging crossbar arrays, offer promis- ing alternatives for addressing the demands of data-intensive computational tasks through in-memory computing of analog vector-matrix multiplication (VMM) operations. However, the propagation of errors due to device and circuit-level imperfec- tions remains a significant challenge. In this study, we introduce MELISO (In-Memory Linear Solver), a comprehensive end-to- end VMM benchmarking framework tailored for RRAM-based systems. MELISO evaluates the error propagation in VMM op- erations, analyzing the impact of RRAM device metrics on error magnitude and distribution. This paper introduces the MELISO framework and demonstrates its utility in characterizing and mitigating VMM error propagation using state-of-the-art RRAM device metrics. 
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